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d a t a sh eet product speci?cation supersedes data of november 1992 file under integrated circuits, ic02 1995 mar 07 integrated circuits philips semiconductors TDA8443A i 2 c-bus controlled yuv/rgb switch
1995 mar 07 2 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A features two rgb/yuv selectable clamped inputs with associated synchronization rgb/yuv matrix 3-state switching with an off-state selectable gain i 2 c-bus or non-i 2 c-bus mode address selection for 7 devices fast switching. general description the TDA8443A is a general purpose two-channel switch for yuv or rgb signals. one channel provides matrixing from rgb to yuv, which can be bypassed. the ic is controlled via i 2 c-bus by seven different addresses or can be used in a non-i 2 c-bus mode. in the non-i 2 c-bus mode, control of the circuit is achieved by dc voltages. quick reference data ordering information symbol parameter conditions min. typ. max. unit v p supply voltage (pin 18) 10.8 12.0 13.2 v i p supply current - 65 90 ma rgb/yuv channels z 19-22 output impedance (pin 19) - 730 w z 20-22 output impedance (pin 20) - 730 w z 21-22 output impedance (pin 21) - 730 w b bandwidth - 3 db; mode 0 or 2 - 25 - mhz +3 db; mode 0 or 2 - 12 - mhz 3 db; mode 1 - 10 - mhz v o(p - p) maximum output amplitude of yuv signals (peak-to-peak value) gain 1 2.1 -- v gain 2 4.2 -- v t amb operating ambient temperature 0 - +70 c type number package name description version TDA8443A dip24 plastic dual in-line package; 24 leads (600 mil) sot101-1
1995 mar 07 3 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A block diagram fig.1 block diagram. handbook, full pagewidth mld003 a4 a3 a2 a1 i c-bus interface/ decoder 2 20 21 23 19 22 18 17 16 15 14 13 24 b3 b2 b1 matrix rgb/yuv clamp clamp clamp clamp pulse generator clamp clamp clamp 2 4 5 6 7 10 11 12 8 9 TDA8443A 3 1 fast switching sel fast switching sync2 b/ (b y) input internal voltage r/ (r y) input g/y input b/ (b y) input sync1 on input g/y input r/ (r y) input channel 1 channel 2 sda scl s0 s1 s2 v gnd sync output clamp pulse generator r/ (r y) input g/y input b/ (b y) input outputs p
1995 mar 07 4 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A pinning symbol pin description sel 1 select input (non-i 2 c-bus mode only) sync2 2 synchronization input for channel 2 fs 3 fast switching input r/ (r - y)in 4 r or (r - y) signal input g/y in 5 g or y signal input b/ (b - y)in 6 b or (b - y) signal input vint 7 internal voltage supply sync1 8 synchronization input for channel 1 on 9 on input r/ - (r - y)in 10 r or - (r - y) signal input g/y in 11 g or y signal input b/ - (b - y)in 12 b or - (b - y) signal input sda 13 serial data input/output; i 2 c-bus scl 14 serial clock input; i 2 c-bus s0 15 address selection input 0 s1 16 address selection input 1 s2 17 address selection input 2 v p 18 supply voltage b/ - (b - y)out 19 b or - (b - y) signal output g/y out 20 g or y signal output r/ - (r - y)out 21 r or - (r - y) signal output gnd 22 ground sync 23 synchronization output clamp 24 clamping pulse generator input/output fig.2 pin configuration. handbook, halfpage TDA8443A mld004 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 sel sync2 fs r/ (r y) in g/y in b/ (b y) in v int sync1 on r/ (r y) in g/y in b/ (b y) in clamp sync gnd r/ (r y) out g/y out b/ (b y) out v s2 s1 s0 scl sda p
1995 mar 07 5 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A functional description the circuit contains two sets of inputs (see fig.1). both channels can receive rgb or yuv signals. each set of inputs has its own synchronization input, which internally generates a pulse to clamp the inputs. the internal clamping pulse can also be controlled by a signal (e.g. a sandcastle pulse) applied to pin 24. the pulse will occur during the time that the signal at pin 24 is between 5.5 and 6.5 v. if both a sync signal and a pin 24 signal are used the signal should be applied to pin 24 via a 1 k w resistor. rgb signals of channel 2 can be matrixed to yuv signals. the outputs can be set in a high impedance off state, which allows the use of seven devices in parallel (i 2 c-bus mode). the circuit can be controlled by an i 2 c-bus compatible microcontroller or directly by dc voltages. the fast switching input can be operated via pin 16 of the peritelevision connector. i 2 c-bus mode the protocol for the devices in i 2 c-bus mode is shown in fig.3. table 1 protocol bit description bit description sta start condition ma2 to ma0 address selection bits; see table 2 ack acknowledge bit d7 channel selection bit; see table 3 d6 matrix selection bit; see table 3 d5 to d3 gain control bits; see table 4 d2 fast switching priority bit; see table 5 d1 and d0 output state control bits; see table 6 sto stop condition fig.3 i 2 c-bus protocol. handbook, full pagewidth sta 1 1 0 1 ma2 ma1 ma0 0 ack d7 d6 d5 d4 d3 d2 d1 d0 ack sto msa003 see table 1.
1995 mar 07 6 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A table 2 address selection notes 1. l = low level input voltage. 2. h = high level input voltage. 3. * = non-i 2 c-bus operation. table 3 mode control bits d7 and d6 table 4 gain setting (see also table 9) matrix equations the relationship between output and input signals of the matrix is as follows: y = 0.3r + 0.59g + 0.11b r - y = 0.7r - 0.59g - 0.11b b - y= - 0.3r - 0.59g + 0.89b address select pins (1)(2) address select bits s2 (pin 17) s1 (pin 16) s0 (pin 15) ma2 ma1 ma0 lll * (3) * (3) * (3) llh001 lhl010 lhh011 hll100 hlh101 hhl110 hhh1 1 1 mode d7 d6 function 0 0 0 channel 2 selected, no matrix 1 0 1 channel 2 selected, matrix active 2 1 0 channel 1 selected - 1 1 not allowed d5 d4 d3 a1 a2, a3, a4 b1, b3 b2 00011 - 1 0.45 0011111 0 1 0 not allowed -- 01111 - 1 0.45 10022 - 1 0.45 1012111 1102211 11121 - 1 0.45
1995 mar 07 7 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A table 5 priority/fast switching bit d2 note 1. x = don't care. d2 fast switching (pin 3) mode 0x (1) 0 to 2, depending on d7, d6 1 0.4 v 2 table 6 output state control bits note 1. x = don't care. d1 d0 pin 9 function 0x (1) x (1) off 10loff 10h on 11x (1) on power-on reset if the circuit is switched on in the i 2 c-bus mode, all bits of d0 to d7 are set to zero. table 7 non-i 2 c-bus mode (s2 = s1 = s0 = l) control mode switched by fs (pin 3) gain settings b1, b3 b2 pin 13 pin 14 pin 1 a1 a4, a3, a2 l l l 2 or 0 1 1 1 1 l l h 2 or 0 1 2 1 1 l h l 2 or 1 1 1 - 1 0.45 l h h 2 or 0 1 1 - 1 0.45 h l l 2 or 0 2 1 1 1 h l h 2 or 0 2 2 1 1 h h l 2 or 1 2 1 - 1 0.45 h h h 2 or 0 2 1 - 1 0.45 table 8 fast switching input (pin 3) fs mode selected 0.4 v mode 2 1 to 3 v mode 0 or mode 1 as set by control table 9 on input (pin 9) on function l off; no output signal; high impedance off-state h function is determined in table 7
1995 mar 07 8 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A limiting values in accordance with the absolute maximum system (iec 134). characteristics v p = 12 v; t amb =25 c; unless otherwise speci?ed. symbol parameter min. max. unit v p supply voltage (pin 18) - 14 v v i(sda) input voltage (pin 13) - 0.3 14 v v i(scl) input voltage (pin 14) - 0.3 14 v v n input voltage any other pin - 0.3 v p + 0.3 v i o(max) maximum output current - 20 ma t amb operating ambient temperature 0 +70 c t stg ic storage temperature range - 55 +125 c t j maximum junction temperature - +125 c symbol parameter conditions min. typ. max. unit supply v p supply voltage (pin 18) 10.8 12.0 13.2 v i p supply current - 65 90 ma rgb/yuv channels g abs absolute gain difference (programmed value) - 010% g rel relative gain difference between y output and the (r - y) and (b - y) channel outputs - 010% between any other two channels - 05 % i i input current - 0.5 1.0 m a | z 19-22 | output impedance (pin 19) - 730 w | z 20-22 | output impedance (pin 20) - 730 w | z 21-22 | output impedance (pin 21) - 730 w b bandwidth - 3 db; mode 0 or 2 - 25 - mhz +3 db; mode 0 or 2 - 12 - mhz 3 db; mode 1 - 10 - mhz t diff mutual time difference at output all inputs of one source connected together -- 25 ns v o(p-p) maximum output amplitude of yuv signals (peak-to-peak value) gain 1 2.1 -- v gain 2 4.2 -- v a ct crosstalk note 1; f i = 5 mhz; between inputs of same source --- 30 db note 1; between same source --- 40 db a off isolation (off state) f i = 10 mhz 50 -- db
1995 mar 07 9 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A g diff(p-p) differential gain at nominal output signals (peak-to-peak value) r - y = 1.05 v (p-p) -- 10 % b - y = 1.33 v (p-p) -- 10 % y = 0.34 v (p-p) -- 10 % s/n signal-to-noise ratio nominal input; b = 5 mhz; note 2 50 -- db svrr supply voltage ripple rejection note 3 30 -- db v o dc output levels during clamping - 5.3 - v synchronization channels g diff gain difference (programmed value) -- 10 % b bandwidth - 3db - 50 - mhz +3 db; gain 1 - 20 - mhz 3 db; gain 2 - 13 - mhz v i(p-p) input amplitude of sync signal for correct operation of clamp pulse generator (peak-to-peak value) 0.2 - 2.5 v | z 23-22 | output impedance (pin 23) - 20 30 w v o(p-p) maximum undistorted output amplitude (pin 23) (peak-to-peak value) 2.5 -- v v o dc output level on top of sync pulse 1.5 1.9 2.4 v i 2 c-bus inputs for sda, scl v ih high level input voltage 3 - v p v v il low level input voltage - 0.3 - 1.5 v i ih high level input current -- 10 m a i il low level input current -- 10 m a i 2 c-bus output for sda (open collector) v ol low level output voltage i ol =3ma -- 0.4 v address selection inputs for s0, s1, s2 v ih high level input voltage 3 - v p v v il low level input voltage - 0.3 - 0.4 v i ih high level input current - 010 m a i il low level input current - 50 - 10 0 m a fast switching input v ih high level input voltage 1 - 3v v il low level input voltage - 0.3 - 0.4 v i ih high level input current - 0 500 m a i il low level input current - 100 -- m a t sw switching time see fig.5 - 10 - ns t d switching delay see fig.5 - 20 - ns symbol parameter conditions min. typ. max. unit
1995 mar 07 10 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A notes 1. crosstalk is defined as the unwanted data transfer from an output, driven at nominal level, to other inputs and outputs on the ic and is expressed as a ratio in dbs. 2. signal-to-noise ratio = 3. supply voltage ripple rejection = select input v ih high level input voltage 3 - v p v v il low level input voltage - 0.3 - 0.4 v i ih high level input current - 010 m a i il low level input current - 50 - 10 0 m a on input v ih high level input voltage 3 - v p v v il low level input voltage - 0.3 - 1.5 v i ih high level input current -- 10 m a i il low level input current -- 10 m a symbol parameter conditions min. typ. max. unit 20log v op p C () v no rms () ---------------------- - b 5 mhz = () 20log v rr supply () v rr at the output () -----------------------------------------
1995 mar 07 11 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A timing characteristics i 2 c-bus load conditions: 4 k w pull-up resistor to +5 v; 200 pf capacitor to gnd; all values are referenced to v ih = 3 v and v il = 1.5 v; see fig.4. note 1. timing t hd;dat deviates from the i 2 c-bus specification. after reset has been activated, a delay of 50 m s must occur before transmission may be resumed. symbol parameter conditions min. typ. max. t buf time bus must be free before start 4.7 -m s t su;sta set-up time for start condition 4.7 -m s t hd;sta hold time for start condition 4.0 -m s t low scl and sda low time 4.7 -m s t high scl high time 4.0 -m s t r scl and sda rise time - 1.0 m s t f scl and sda fall time - 0.3 m s t su;dat data set-up time (write) 250 - ns t hd;dat data hold time (write) note 1 1.0 -m s t su;ack acknowledge set-up time - 2 m s t hd;ack acknowledge hold time 0 -m s t su;sto set-up time for stop condition 4.7 -m s fig.4 i 2 c-bus timing diagram. handbook, full pagewidth mld005 sda (write) scl t buf t su; sta t hd; sta t low t f t r t hd; dat t su; ack t hd; ack t low t su; sto t high t su; dat
1995 mar 07 12 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A fig.5 fast switching signal diagram. handbook, full pagewidth mld006 fast switching input signal output signal (yuv) switching delay switching time 90 % 50 % 10 %
1995 mar 07 13 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A application information table 10 channel input/output information input 1 input 2 output mode d5 d4 d3 y = 0.34 v - y = 0.34 v 2111 u= - 1.33 v u = - 1.33 v v= - 1.05 v v = - 1.05 v s = 0.3 v s = 0.6 v - r = 0.75 v y = 0.34 v 1111 g = 0.75 v u = - 1.33 v b = 0.75 v v = - 1.05 v s = 0.3 v s = 0.6 v y = 0.34 v - y = 0.68 v 2100 u= - 1.33 v u = - 2.66 v v= - 1.05 v v = - 2.10 v s = 0.3 v s = 0.6 v - r = 0.75 v y = 0.68 v 1100 g = 0.75 v u = - 2.66 v b = 0.75 v v = - 2.10 v s = 0.3 v s = 0.6 v y = 0.34 v - y = 0.34 v 2101 u= - 1.33 v u = - 1.33 v v= - 1.05 v v = - 1.05 v s = 0.3 v s = 0.6 v - y = 0.34 v y = 0.34 v 0101 u= - 1.33 v u = - 1.33 v v= - 1.05 v v = - 1.05 v s = 0.3 v s = 0.6 v y = 0.34 v - y = 0.68 v 2110 u= - 1.33 v u = - 2.66 v v= - 1.05 v v = - 2.10 v s = 0.3 v s = 0.6 v - y = 0.34 v y = 0.68 v 0110 u= - 1.33 v u = - 2.66 v v= - 1.05 v v = - 2.10 v s = 0.3 v s = 0.6 v
1995 mar 07 14 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A fig.6 application diagram (example). handbook, full pagewidth mld007 1 nf 4.7 k w v p clamp 24 sync 23 gnd 22 (r y) 21 y 20 (b y) 19 18 s2 17 s1 16 s0 15 scl 14 sda 13 v p 1 2 3 4 5 6 7 8 9 10 11 12 4.7 m f 47 nf 47 nf 47 nf 22 nf 4.7 m f 47 nf 47 nf 47 nf (r y) y (b y) on sync1 internal voltage sel channel 1 (colour decoder) outputs outputs 7 9 11 13 15 17 19 8 101214161820 b g r fs sync2 channel 2 (peritelevision connector) TDA8443A
1995 mar 07 15 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A input clamps the r, g, b respectively (r - y), y and (b - y) video signals are ac-coupled to the ic where they are clamped on the black level. the timing information for this clamping action is derived from the associated synchronization signal sync, which could also consist of the composite video information signal cvbs. the syncsignal is ac-coupled to the ic where it is clamped on top-sync level, information obtained from this action is used to generate the clamp pulses. the clamp pulses can be generated in two ways: 1. using the sync information (internal clamping) the sync information is clamped on top-sync and the information obtained from this action is used to switch an internal current source at pin 24. pin 24 should be connected to v p via a 4.7 k w resistor, and a 1 nf capacitor to ground. during video scan the voltage at pin 24 will be high (equals positive supply voltage). during the synchronization pulses the voltage at pin 24 will drop to zero because of the current sink (2.5 ma). when the synchronization pulse is over, the current source is switched off and the voltage at pin 24 will rise to its higher level. because of the time constant at pin 24, the restoration will take some microseconds. the voltage at pin 24 is also sensed internally and at the time it is between 0.456v p and 0.544v p , a time pulse is generated and used for the clamping action. 2. using a sandcastle pulse (external clamping) if an associated sandcastle pulse is available, it can also be used as a clamping pulse. in this event the sandcastle pulse should be connected to pin 24, the top of the clamping pulse should be between 0.544v p and 0.456v p . the timing of the internal clamping pulse will be equal to the timing of the higher part of the sandcastle pulse. if the sync signal is also connected, the current sink will also become active during the synchronization pulses. this means that the sandcastle pulse should be connected to pin 24 via a 1k w dropping resistor. in this event only the sandcastle pulse at pin 24 will be influenced during sync pulses, but the sandcastle pulse at the sandcastle source will be unchanged. fig.7 clamping circuit. tolerance on v1 and v2 is given by d r/r and d v p /v p . the diffusion process gives d r/r (max) = 1.5%. handbook, halfpage mea623 on when current sync = 2.5 ma off when current sync = 0 ma pin 24 9.4 k w 1.8 k w 9.4 k w v p v1 v2 clamp pulse signal v1 = 0.544 v p v2 = 0.456 v p
1995 mar 07 16 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A package outline unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot101-1 92-11-17 95-01-23 a min. a max. b w m e e 1 1.7 1.3 0.53 0.38 0.32 0.23 32.0 31.4 14.1 13.7 3.9 3.4 0.25 2.54 15.24 15.80 15.24 17.15 15.90 2.2 5.1 0.51 4.0 0.066 0.051 0.021 0.015 0.013 0.009 1.26 1.24 0.56 0.54 0.15 0.13 0.01 0.10 0.60 0.62 0.60 0.68 0.63 0.087 0.20 0.020 0.16 051g02 mo-015ad m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 24 1 13 12 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. z max. (1) (1) (1) dip24: plastic dual in-line package; 24 leads (600 mil) sot101-1
1995 mar 07 17 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A soldering plastic dual in-line packages b y dip or wave the maximum permissible temperature of the solder is 260 c; this temperature must not be in contact with the joint for more than 5 s. the total contact time of successive solder waves must not exceed 5 s. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). if its temperature is below 300 c, it must not be in contact for more than 10 s; if between 300 and 400 c, for not more than 5 s. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1995 mar 07 18 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A notes
1995 mar 07 19 philips semiconductors product speci?cation i 2 c-bus controlled yuv/rgb switch TDA8443A notes
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(021)577035/5874546. philippines: philips semiconductors philippines inc, 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (02)810 0161, fax. (02)817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366. singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494. spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (02)388 7666, fax. (02)382 4382. thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (662)398-0141, fax. (662)398-3319. turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 2770, fax. (0212)282 6707 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md, eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-724825 scd38 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 533061/1500/02/pp20 date of release: 1995 mar 07 document order number: 9397 750 00021

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